An integrated circuit chip includes a plurality of active components and passive components interconnected based on actual design requirements. For integrating and interconnecting multiple components, an integrated circuit chip commonly has a plurality of metal wiring layers. The topography of each metal wiring layer is uneven when a hillock issue occurs during fabrication, which usually reduces the yield rate. In an instance, a contact via located at where the hillock is fails to extend to the predetermined depth so that an open circuit or an undesirable short circuit is generated.